Semiconductor device and method for fabricating the same
US6597016B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2000 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jan 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An Si1−yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterounction junction is formed between the Si and Si1−yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the Si1−yGey layer can be suppressed. As a result, the Si/Si1−yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.