Process for packaging a chip with sensors and semiconductor package containing such a chip
US6597020B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Aug 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for packaging an integrated circuit chip that has a front face with sensors located in a central region and electrical connection areas located in a region that lies between at least one edge of the chip and the central region. According to the method, a rear face of the chip is cemented to a front face of a substrate that includes through-holes, with the rear face of the substrate including electrical connection areas that pass in front of the through-holes such that the through-holes are located laterally with respect to the edge of the chip. The electrical connection areas on the front face of the chip are connected to the electrical connection areas on the substrate through the through-holes, and the chip is embedded in an optically transparent encapsulating material so as to form an encapsulating block on the same side as the front face of the substrate. The substrate is cut around the encapsulating block, following the perimeter of the encapsulating block. Also provided is a semiconductor package that includes an integrated circuit chip, a substrate, electrical connectors, and an encapsulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.