Encapsulated metal structures for semiconductor devices and MIM capacitors including the same

US6597068B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kevin S. Petrarca · Newburgh, US
• Donald F. Canaperi · Bridgewater, US
• Mahadevaiyer Krishnan · Hopewell Junction, US
• Kenneth J. Stein · Sandy Hook, US
• Richard P. Volant · New Fairfield, US

Key dates

• Filing date: Dec 28, 2001
• Grant date: Jul 22, 2003
• Expiry date: Dec 28, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/692
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.