Clock synchronization device
US6597298B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock synchronization device divides a digital-to-analog converting unit into main and sub digital-to-analog converters and operates both main and sub digital-to-analog converting units if an output voltage of the digital-to-analog converting unit is lower than a reference voltage based on a voltage obtained when the delay rate of a variable delay line VDL is sharply increased or operates only the main digital-to-analog converting unit if the output voltage of the digital-to-analog converting unit is higher than the reference voltage. As a result, the clock synchronization device can make the output voltage of the digital-to-analog converting unit be linear with respect to a digital code, thereby improving a jitter property in a band with a very large gain of the variable delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.