RTL power analysis using gate-level cell power models
US6598209B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jun 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for analyzing the power consumption of a behavior description of an electrical design includes a structural element library including a set of technology-independent structural macro elements, a macro power model module providing macro power models for one or more of the structural macro elements in the structural element library, and a power estimation module providing a power consumption value of the electrical design using a netlist of interconnected components representative of the electrical design, and the macro power models. The macro power models are associated with corresponding power models in a user-specified gate-level power model library. The power analysis system enables behavior level or RTL power analysis using a user-specified gate-level cell power model library containing arc-based or pin-based power model descriptions or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.