Static timing analysis validation tool for ASIC cores
US6598213B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jan 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of characterizing worst case timing performance includes the steps of receiving as input a netlist of a core, performing a parasitic extraction on the netlist to generate a first standard parasitic extraction format file for a first assumed top metal layer over the core, performing a parasitic extraction on the netlist to generate a second standard parasitic extraction format file for a second assumed top metal layer over the core, calculating a minimum timing value from each delay arc of the first standard parasitic extraction format file, calculating a maximum timing value from each delay arc of the second standard parasitic extraction format file, and merging the minimum timing value calculated from each delay arc of the first standard parasitic extraction format file and the maximum timing value of each delay arc calculated from the second standard parasitic extraction format file to generate an output file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.