Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode
US6599808B2 · kind B2 · utility
12Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2001 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Sep 12, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/932
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Method for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce and increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.