Vertical field-effect semiconductor device with buried gate region
US6600192B1 · kind B1 · utility
40Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Apr 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
Abstract
A buried gate region, a buried gate contact region and a gate contact region are provided on an SiC substrate. Thereby, a depletion layer expands in the channel region, and a high withstand voltage is attained in the normally off state. By applying a voltage of the built-in voltage or less to a gate, the depletion layer in the channel region becomes narrower and an ON-state resistance becomes low. Furthermore, when a voltage of the built-in voltage or more is applied to the gate, holes are injected from the gate so as to cause the conductivity modulation, and the ON-state resistance becomes further low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.