Patent · US Expired

Line segmentation in programmable logic devices having redundancy circuitry

US6600337B2 · kind B2 · utility

14Cited by

10References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Triet Nguyen · San Jose, US
Changsong Zhang · San Jose, US
David Jefferson · San Jose, US

Key dates

Filing date	Apr 26, 2001
Grant date	Jul 29, 2003
Priority date	—
Expiry date	Apr 26, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/70
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.