Dynamically reconfigurable data space
US6601160B2 · kind B2 · utility
2Cited by
103References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Jul 29, 2003 |
| Priority date | — |
| Expiry date | Jan 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.