Heterointegration of materials using deposition and bonding
US6602613B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2001 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Jan 17, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24917
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.