MOS-gated power device with doped polysilicon body and process for forming same
US6602768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2002 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Jan 10, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/914
Abstract
An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101a of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer 112 on the upper surface overlying the gate and source regions 114, and a heavily doped drain region of the first conduction type 115. The improvement includes body regions 301 containing heavily doped polysilicon of the second conduction type disposed in a well region 107 at the upper surface of the monocrystalline substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.