Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer
US6602779B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2002 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a hard mask layer formed upon the dielectric layer. The hard mask layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency power of from about 100 to about 500 watts per square centimeter substrate area. The hard mask layer provides for attenuated abrasive damage to the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.