Integrated semiconductor memory configuration

US6603164B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Marcus Kastner · Ottobrunn, DE
• Thomas Mikolajick · Birkenfeld, DE

Key dates

• Filing date: Dec 31, 2001
• Grant date: Aug 5, 2003
• Expiry date: Dec 31, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be addressed by the selection transistor. The capacitors of successive memory cells are formed alternately on the front and rear sides of a substrate wafer.