Semiconductor device
US6603190B2 · kind B2 · utility
12Cited by
9References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a plated heat sink (PHS) layer on the back surface, preventing a short circuit between a bonding wire, and a first metal layer. A method of making a semiconductor device including forming a catalyst layer on a bottom of a first separation groove in the front surface of a semiconductor substrate, and forming the first metal layer selectively in the first separation groove by electroless plating, using the catalyst layer as a catalyst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.