Method and apparatus for reduction of noise sensitivity in dynamic logic circuits
US6603333B2 · kind B2 · utility
6Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Dec 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for protecting dynamic logic circuits from the effects of noise at the inputs to the dynamic logic circuits is disclosed. Parallel current flow or evaluate paths which couple an output node through a common node to a low voltage or ground rail include extra transistors in the current flow or evaluate path to allow the inputs to be protected while maintaining the operation and integrity of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.