Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method
US6603681B2 · kind B2 · utility
3Cited by
2References
18Claims
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Key dates
| Filing date | Oct 31, 2001 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Oct 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.