Verifying on-chip decoupling capacitance using transistor and capacitor surface area information
US6604226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2001 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Dec 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for verifying on-chip decoupling capacitance using transistor and capacitor surface area information is provided. The technique broadly includes determining a surface area of a transistor, determining a surface area of a decoupling capacitor, comparing the surface area of the transistor to the surface area of the decoupling capacitor to obtain a surface area ratio, and verifying whether there is enough decoupling capacitance based on the surface area ratio. Further, the present invention also provides a technique for determining when and how to redesign a microprocessor in order to have sufficient decoupling capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.