Layout technique for semiconductor processing using stitching
US6605488B1 · kind B1 · utility
5Cited by
3References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2000 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/802
Abstract
A technique and structure for simplifying the stitching process is disclosed. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout method for a row/column decoder that reduces the number of blocks when stitching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.