Method and circuit for processing output data in pipelined circuits
US6606272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit according to the present invention includes a plurality of data registers each coupled between the output terminal and a data bus. Each data register stores successive data bits received serially from the data bus. The circuit also includes a plurality of output enable signals each coupled to a corresponding data register. Additionally, the circuit includes a mode select circuit to program the plurality of output enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width greater than the first pulse width. The circuit may be included as part of a memory circuit in a memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.