Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit
US6606699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2001 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Feb 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for concurrently executing controller single instruction single data (SISD) instructions and single instruction multiple data (SIMD) processing element instructions comprising a combined controller and processing element. At least first and second simplex instructions each comprise a mode of operation bit, said mode of operation bit in the first simplex instruction specifying a controller SISD operation for execution by the controller, and the mode of operation bit in the second simplex instruction specifying a procesing element SIMD operation for execution by the processsing element. A very long instruction word (VLIW) contains said at least first and second simplex instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.