Process to manufacturing tight tolerance embedded elements for printed circuit boards
US6606792B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 2000 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | May 25, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process for forming printed circuit substrates incorporating impedance elements in which a pattern of impedance elements and a conductor pattern are incorporated on an insulating support. The process involves depositing a layer of an impedance material on a first surface of a sheet of an electrically highly conductive material and attaching a second surface of the sheet of highly conductive material to a support. Then one applies a layer of a photoresist material onto the layer of impedance material with imagewise exposure and development. After etching away the portion of the impedance layer material underlying the removed nonimage areas of the photoresist material, a pattern of impedance elements remain on the sheet of highly conductive material. Thus printed circuit board with impedance elements can be manufactured to a high degree of electrical tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.