MIS transistors with a metal gate and high-k dielectric and method of forming

US6607950B2 · kind B2 · utility

Assignee

• INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW · BE

Inventors

• Kirklen Henson · Gastonia, US
• Rita Rooyackers · Kessel-Lo, BE
• Serge Vanhaelemeersch · Leuven, BE
• Goncal Badenes · Sabadell, ES

Key dates

• Filing date: Mar 30, 2001
• Grant date: Aug 19, 2003
• Expiry date: Mar 30, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.