Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells

US6608365B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Weidan Li · San Jose, US
• Benjamin Mbouombouo · San Jose, US
• Johann Leyrer · Munich, DE

Key dates

• Filing date: Jun 4, 2002
• Grant date: Aug 19, 2003
• Expiry date: Jun 4, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/66

Abstract

An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.