Weidan Li
15Patents
8h-index
32Co-inventors
68Inventor score
Filing activity: Dec 16, 1998 → Sep 23, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6423628B1 | Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines | Electricity | 193 | Expired |
| US7321254B2 | On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method | Electricity | 22 | Expired |
| US6756674B1 | Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same | Electricity | 17 | Expired |
| US6807656B1 | Decoupling capacitance estimation and insertion flow for ASIC designs | Physics | 16 | Expired |
| US6391768B1 | Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure | Electricity | 15 | Expired |
| US6608365B1 | Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells | Electricity | 13 | Expired |
| US6329720A | Tungsten local interconnect for silicon integrated circuit structures, and method of making same | Electricity | 8 | Expired |
| US7000163B1 | Optimized buffering for JTAG boundary scan nets | Physics | 8 | Expired |
| US6569751B1 | Low via resistance system | Electricity | 4 | Expired |
| US8946890B2 | Power/ground layout for chips | Electricity | 2 | Active |
| US7181712B2 | Method of optimizing critical path delay in an integrated circuit design | Physics | 1 | Expired |
| US9449709B1 | Volatile memory and one-time program (OTP) compatible memory cell and programming method | Physics | 1 | Active |
| US8921938B1 | Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells | Electricity | 1 | Active |
| US6794756B2 | Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines | Electricity | 1 | Expired |
| US6893962B2 | Low via resistance system | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.