I/O architecture/cell design for programmable logic device
US6608500B1 · kind B1 · utility
18Cited by
34References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17788
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising an input/output circuit and a programmable logic device. The input/output circuit may be configured to (i) connect to an end of a bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate said one or more control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.