Low-power circuit structures and methods for content addressable memories and random access memories
US6608771B2 · kind B2 · utility
4Cited by
2References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 20, 2001 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for associating an address with data. The method includes precharging a matchline connected to a plurality of tag match functions to a first potential, wherein each tag match function comprises one or more match logic devices, discharging two tag lines for a first tag bit to ground, and reading a plurality of tag bits and corresponding data bits onto a plurality of tag lines and a plurality of data lines respectively. The method further includes determining a match between the tag bits and data bits, and pulling the matchline to a second potential upon determining a match for each of the tag bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.