Multi-channel serial port with programmable features
US6609163B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2000 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Dec 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using &mgr;-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.