Latch clustering for power optimization
US6609228B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2000 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.