Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
US6610150B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2000 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Jan 13, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.