Amorphous barrier layer in a ferroelectric memory cell
US6610549B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2000 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Jul 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ferroelectric cell, particularly one integrated on a silicon substrate, comprising an amorphous barrier layer interposed between the ferroelectric stack and the silicon. Preferably, the ferroelectric stack includes conductive metal oxide electrodes sandwiching the ferroelectric layer. The metal oxide may act as a templating layer to crystallographically orient the ferroelectric layer. Alternatively, the electrodes and ferroelectric layer may be polycrystalline. The amorphous barrier layer may be composed of an intermetallic alloy, such as Ti3Al, a metal-metalloid, such as Pd—Si, a combination of early and later transition metals, such as Ti—Ni, and other related compound metal systems, such as (Ti, Zr)—Be, that form amorphous metals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.