Memory circuit for preventing rise of cell array power source
US6611472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2001 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Feb 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is that, in a memory circuit comprising a cell array and peripheral circuit, the cell array power source is supplied to a circuit which operates during the power-down mode in addition to the cell array. The circuit which operates during the power-down mode is, for example, a self-refresh circuit. A dynamic memory requires refreshing operations in fixed intervals even during the power-down mode. Therefore, the self-refresh circuit is operating even during the power-down mode. Thus, by supplying the cell array power source to the self-refresh circuit, it is possible to consume a prescribed quantity of current from the cell array power source generation circuit to an extent of being able to maintain the level thereof even during the power-down mode. The cell array power source may be maintained within an appropriate voltage range thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.