Test circuit for memory
US6611929B1 · kind B1 · utility
1Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 20, 2000 |
| Grant date | Aug 26, 2003 |
| Priority date | — |
| Expiry date | Jan 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit for memory having plural memory cells and address latches responsive to addressing circuitry for reading/writing to said memory cells in a normal mode, has first connecting circuitry for connecting the address latches to form a linear feedback shift register. The linear feedback shift register is responsive to a clock signal to provide a sequence of addresses for testing the memory in a test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.