Real-time decoder for scan test patterns

US6611933B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bernd Koenemann · San Jose, US
• Carl Barnhart · Tucson, US
• Brion Keller · Binghamton, US

Key dates

• Filing date: Apr 12, 2000
• Grant date: Aug 26, 2003
• Expiry date: Apr 12, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318547
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and by increasing the effective bandwidth of the scan-load operation. The reduced test data volume and corresponding test time are achieved by integrating a real-time test data decoder or logic network into each integrated circuit chip. The apparatus, servicing a plurality of internal scan chains wherein the number of said internal scan chains exceeds the number of primary inputs available for loading data into the scan chains, includes: a) logic network positioned between the primary inputs and the inputs of the scan chains, the logic network expanding input data words having a width corresponding to the number of the primary inputs, and converting the input data words into expanded output data words having a width that corresponds to the number of the internal scan chains; and b) coupled to the internal scan chains, registers loaded with bit values provided by the expanded output data words while data previously loaded into the scan chains shifts forward within the scan chains by one bit p…