Optical chip packaging via through hole
US6613597B2 · kind B2 · utility
6Cited by
7References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of packaging an optical chip or an optical chip with an electronic chip that allows for close connections between the two chips. The method reduces parasitic capacitance and inductance, and provides unobstructed optical access while allowing for connection of a heat sink to the electronic chip for cooling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.