ASIC routing architecture with variable number of custom masks
US6613611B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jul 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
Abstract
A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC. Other embodiments allow a determination to be made of the ideal number of custom mask steps, taking into consideration performance, cost, time, and routability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.