Methods of forming self-aligned contact pads using a damascene gate process
US6613621B2 · kind B2 · utility
42Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2001 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jul 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.