Method for fabricating an integrated semiconductor circuit

US6613624B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Helmut Wurzer · Dresden, DE

Key dates

• Filing date: Jul 24, 2002
• Grant date: Sep 2, 2003
• Expiry date: Jul 24, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0147

Abstract

Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of the electrons. Transistors in semiconductor circuits having both a memory region and a logic region are fabricated either with different dopings for pMOS and nMOS transistors in the logic region (dual work function) or with a common source/drain electode in the memory region (borderless contact). In the latter case, all the transistors of the semiconductor circuit receive the same gate doping. A method is proposed by which it is possible to realize dual work function and borderless contact on a semiconductor substrate simultaneously in a simple manner.