Semiconductor non-volatile memory device having a NAND cell structure
US6614070B1 · kind B1 · utility
99Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Sep 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND stack array (95′) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.