Microelectronic device package with conductive elements and associated method of manufacture
US6614092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2001 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Aug 10, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover attached to the substrate and at least partially enclosing the first and second device features and the conductive link. The external cover can have a composition substantially identical to the composition of the conductive links and the external cover can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.