Thermally enhanced IC chip package
US6614660B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thermally enhanced IC chip package has a dielectric substrate member with conductive circuit patterns on top and bottom surfaces thereof and an opening therethrough. An IC chip having active and inactive sides is received in the opening. The active side of the chip and the top surface of the substrate face to a same direction and electrically connect each other. A thermally and electrically conductive adhesive layer is disposed on the inactive side of the chip and the bottom surface of the substrate in a completely enclosing shape around the opening. A thermally and electrically conductive planar member is attached to the thermally and electrically conductive adhesive layer. A molding material encapsulates the chip, the opening and the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.