Semiconductor integrated circuit and nonvolatile memory element
US6614684B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.