FIR filter architecture for 100Base-TX receiver
US6614842B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | May 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A 100Base-TX receiver employs a finite impulse response (FIR) filter to provide both equalization and insertion loss compensation for an MLT-3 input signal. The FIR filter includes three delay stages, each delaying the input signal with an 8 ns delay (the period of one data cycle of the MLT-3 input signal), a set of three amplifiers for amplifying the delay stage outputs with gains C1, C2 and C3, and a summer for summing the outputs of the three amplifiers to produce a compensated, equalized MLT-3 signal. A low-pass filter filters the FIR filter output signal, and a data slicer digitizes the low-pass filter output during each data cycle to produce data representing the incoming MLT-3 as having one of six levels. An adaptive control signal processes the slicer output data to determine how to set the gains C1, C2 and C3 of the three FIR amplifiers to provide the correct amount of equalization and compensation. The adaptive control circuit also processes the slice data to adaptively adjust the phase of a clock signal controlling timing of the data slicer, to adaptively adjust an amount of baseline wander compensation provided to the MLT-3 signal, and to determine the value of data con…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.