Method for identifying the best tool in a semiconductor manufacturing process
US6615101B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Aug 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for identifying a best tool from a plurality of tools that perform a same operation in a semiconductor fabrication line that includes the steps of determining a first median yield for each of the plurality of tools within a first time interval, weighting the first median yield based on a total number of wafers processed by each of the plurality of tools within the first time interval, determining a second median yield for the semiconductor fabrication line over the first time interval, obtaining a weighted yield difference for each of the plurality of tools relative to the second median yield, and outputting the weighted yield difference for each of the plurality of tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.