Efficient implementation of first-in-first-out memories for multi-processor systems
US6615296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2001 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Jan 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.