First and next error identification for integrated circuit devices
US6615374B1 · kind B1 · utility
23Cited by
8References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device performs first and next error identification. An error condition associated with an integrated circuit device function is detected. Whether the detected error condition is a first detected error condition is determined, and, if so, the detected error condition is identified as the first detected error condition. Otherwise, the detected error condition is identified as a next detected error condition. A first detected error condition may be recorded in a first error status register, and a next detected error condition may be recorded in a next error status register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.