Douglas R. Moran
18Patents
7h-index
54Co-inventors
69Inventor score
Filing activity: Oct 31, 1991 → Sep 20, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6594756B1 | Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor | Physics | 34 | Expired |
| US6457068B1 | Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation | Physics | 25 | Expired |
| US7139890B2 | Methods and arrangements to interface memory | Physics | 23 | Expired |
| US6615374B1 | First and next error identification for integrated circuit devices | Electricity | 23 | Expired |
| US6618770B2 | Graphics address relocation table (GART) stored entirely in a local memory of an input/output expansion bridge for input/output (I/O) address translation | Physics | 14 | Expired |
| US8522322B2 | Platform firmware armoring technology | Physics | 12 | Active |
| US7861024B2 | Providing a set aside mechanism for posted interrupt transactions | Physics | 7 | Active |
| US6738869B1 | Arrangements for out-of-order queue cache coherency and memory write starvation prevention | Physics | 6 | Expired |
| US9092632B2 | Platform firmware armoring technology | Physics | 4 | Active |
| US9690353B2 | System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request | Emerging Cross-Sectional Technologies | 3 | Active |
| US8650427B2 | Activity alignment algorithm by masking traffic flows | Physics | 3 | Active |
| US7610611B2 | Prioritized address decoder | Physics | 3 | Active |
| US9152205B2 | Mechanism for facilitating faster suspend/resume operations in computing systems | Physics | 2 | Active |
| US9766683B2 | Interconnect to communicate information uni-directionally | Emerging Cross-Sectional Technologies | 1 | Active |
| US9477627B2 | Interconnect to communicate information uni-directionally | Emerging Cross-Sectional Technologies | 1 | Active |
| US5278800A | Memory system and unique memory chip allowing island interlace | Physics | 1 | Expired |
| US9098561B2 | Determining an effective stress level on a processor | Physics | 0 | Active |
| US8145816B2 | System and method for deadlock free bus protection of resources during search execution | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.