Method and apparatus for holding failing information of a memory built-in self-test
US6615378B1 · kind B1 · utility
12Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A network interface controller arrangement and a method of testing a memory arrangement uses a register to hold failing information from a memory built-in self test (MBIST). The register is accessible to a processor through a bus interface of the network interface controller. The processor performs a read operation through the bus interface upon the completion of an MBIST to examine the failing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.