Blocked net buffer insertion
US6615401B1 · kind B1 · utility
8Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2002 |
| Grant date | Sep 2, 2003 |
| Priority date | — |
| Expiry date | Mar 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of determining a desired connection path between a pair of points of a net separated by one or more blockages, while reducing path delays and ramp time violations and without placing buffers within any of the blockages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.