Method for fabricating a full depletion type SOI device
US6617202B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | Sep 9, 2003 |
| Priority date | — |
| Expiry date | Dec 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0323
Abstract
Disclosed is a method for SOI device, and particularly to a method for fabricating a full depletion type SOI device capable of minimizing a change in a threshold voltage of transistor according to a change in a thickness of semiconductor layer. The disclosed method for fabricating a full depletion type SOI device comprises: preparing a SOI wafer having a stack structure consisted of a base substrate, a buried oxide film, and a semiconductor layer, forming a dummy gate on an active region of the semiconductor layer, forming source/drain regions on an active region of the semiconductor layer at both sides of the dummy gate, depositing an insulating layer over the dummy gate and the semiconductor layer, polishing the insulating film using the dummy gate as a polishing stop layer, removing the dummy gate, etching a predetermined thickness of semiconductor layer exposed by removing the dummy gate, growing a delta doped silicon film and a silicon film doped in a low concentration on a remaining part of the semiconductor layer, the total thickness thereof being equal to that of the source/drain regions, and forming a gate having a gate oxide film on the silicon film doped in a low concent…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.